1. Field of the Invention
The invention relates in general to a method of fabricating a local interconnect in an integrated circuit (IC), and more particularly, to a method of fabricating a local interconnect by transforming refractory metal oxide into a semiconductor or a conductor.
2. Description of the Related Art
As integrated circuits are developed towards a direction of higher and higher integration, the number of interconnects required for electrical connection between devices or electrodes is increased. However, the surface area of a chip available for forming interconnects becomes more and more limited due to the shrinking dimensions of devices. Therefore, two or more conductive layers are designed to meet the requirements of high integration and limited surface area. For example, while fabricating a complex device such as a microprocessor, at least four or five metal layers are required to achieve the electrical connection between electrodes or devices of the microprocessor.
In the design of a sub-micron integrated circuit, a local interconnect is formed to improve packing density. In circuit layout design, a local interconnect is used for horizontal connection between closely spaced devices.
Various types of local interconnects have been developed and applied in integrated circuit design. The material used for fabricating a local interconnect includes refractory metal silicide on poly-silicon, single or double doped poly-silicon, multi-layered refractory metal which is partially converted into silicide, or refractory metal formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
FIGS. 1A-1D show a conventional process for fabricating a local interconnect. In FIG. 1A, a semiconductor substrate 10 having a shallow trench isolation 11 formed therein is provided. A gate oxide layer 12 is formed on the substrate 10, and a first gate electrode 13 and a second gate electrode 14 are formed on the gate oxide layer 12. A spacer 15 is formed on each sidewall of the first gate electrode 13 and the second gate electrode 14. An extension surface of the electrodes 13 and 14 are left exposed. The material of the first gate electrode 13 and the second gate electrode 14 includes doped poly-silicon, whereas the material of the spacer 15 includes silicon oxide.
In FIG. 1B, a self-aligned silicide (salicide) layer 16 is formed on the exposed surface of the first gate electrode 13, the exposed surface of the second gate electrode 14, and the exposed substrate 10. In a conventional process of forming salicide, a metal layer, for example, a titanium layer with a thickness of about 200-1000 .ANG., is formed over the surface of the substrate 10 by DC magnetron sputtering. Under a high temperature, the metal layer reacts with the poly-silicon of the first and second gate electrodes 13, 14 and the silicon of the exposed substrate 10 and is transformed into a metal silicide layer 16, for example, titanium silicide (TiSi.sub.2). The remaining metal layer, which does not form a suicide, is then removed.
In FIG. 1C, a titanium nitride layer 17a is formed over the surface of the substrate 10 by reactive sputtering. A photo-resist layer 18 is formed and patterned to cover the second gate electrode 14, and about a half of the region between the first and the second gate electrodes 13, 14.
In FIG. 1D, the titanium nitride 17a (shown in FIG. 1C) is removed by etching, using the photo-resist layer 18 as a mask. The subsequent processes, for example, removing the photo-resist layer 18, are then performed to complete the formation of the local interconnect. The resultant pattern of the titanium nitride layer is denoted as 17b as shown in the figure.
Processes such as deposition of titanium nitride, patterning and etching are required for the above method, the result of which is poor controllability. There is thus a need for a process of forming a local interconnect that is simpler and more controllable. In addition, an uneven topography of the device results from the prior processes, and that is disadvantageous to the subsequent process. There is thus a need for a process resulting in a more even topography.